SanDisk And Toshiba To Produce 3D Chips

by Trefis Team
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After Samsung Electronics (PINK:SSNLF) rolled out the first 3D storage chips in 2013, storage chip manufacturers SK Hynix and Micron Technologies (partnered with IBM) revealed their plans to develop and mass-produce their own 3D chips. Last week, SanDisk Corporation (NASDAQ:SNDK) and Toshiba announced their joint decision to produce 3D chips on a mass scale. [1] SanDisk has been focused on expanding its planar (or 2D) technology with the launch of the new 15 nanometer chips in April. [2] However, the constant reduction in process node sizes of conventional chips has made lithographic work more complex. Additionally, the gain in storage capacity doesn’t necessarily justify the massive cost involved in developing the technology, as smaller node sizes (<20 nanometers) begin to lose efficiency. 3D NAND chips aim to combat these problems with vertically stacking chips rather than planar arrangement in conventional chips.

See our full analysis for SanDisk’s Stock

Why 3D?

Every year, the advancement of technology has led chip makers to accommodate more data on chips while simultaneously shrinking their  physical size. But reducing the size of process nodes further from the commonly used 20 or 19 nanometers to 10 nanometers has proved challenging and has affected the performance of these chips. Although the idea of 10 nanometer process nodes hasn’t been completely ousted, it is likely that different cell design methods gain popularity among manufacturers. In addition to becoming a very challenging task, the cost involved to further reduce the size of process nodes may outweigh the storage space/capacity gained.

The 3D card involves a new technology that aims to solve that problem; 3D technology stacks the chips vertically in an array, unlike planar NAND technology where the chips are arranged like a grid. Moreover, 3D chips do not require extremely precise lithography, which makes them cheaper to produce than advanced planar NAND chips. Samsung claims to produce V-NAND (or Vertical-NAND) chips which are 2-10 times as more durable and reliable than planar NAND chips. Additionally, these chips provide twice the scalability of the current 20-nanometer planar NAND flash. [3] Furthermore, Samsung’s 3D solid state drives (SSD) consume 20% less power than planar multi-level cell NAND-based drives. [4]

Where SanDisk Stands On 3D

SanDisk and Toshiba entered into an agreement where Toshiba will demolish its existing Fab 2 manufacturing plant in Japan and build a new wafer facility which will produce 3D chips. The deal is reportedly worth Japanese yen 500 billion ($4.84 billion). [5] Toshiba will cover the initial 40 billion yen ($390 million) in expenses of converting the existing facility into a new one and SanDisk will then later invest in the facility. [1] The new facility is scheduled to be completed by 2015 and production could start by early 2016.

The SanDisk-Toshiba chips will hit the market significantly later than competitors Samsung (2o13), Hynix (early 2014) and Micron (2014). The main reason for this time lag is SanDisk’s continued focus on small size (<19 nanometer) chips and 2D technology. Experts believe that it is not a question of if, but when the 3D chips will replace the existing technology. [6]

The added durability, lower cost of production and increased scalability suggests that 3D or vertically stacked chips could be the future of storage blocks, although it will be a few years before the technology becomes mainstream. Initially, the V-NAND offered by Samsung had nearly the same storage density as a corresponding conventional planar NAND. [7] But with the increase in demand, the density gap has increased significantly. Samsung plans to invest a further $4 billion in its chip manufacturing division through March 2015, giving it a significant head start in this area.

The mass production of 3D chips could have long term benefits for SanDisk as the demand for data is only going to continue to increase. With the kind of scalability offered by 3D technology, it seems like it could ultimately replace the conventional planar technology. A possible downside for SanDisk could be if the 3D chips produced by Samsung and Hynix gain popularity before SanDisk-Toshiba even begin production. Given the very limited market presence of 3D chips right now, its difficult to predict how soon the market adopts the new chips. However, in the long run, storage chip manufacturers are likely to rely heavily on vertical stacking.

If 3D chips gain traction from next year and become more widely adopted in internal storage of smartphones, wearable portable devices and laptops, it could lead to a reduction in SSD prices. If SSD prices fall to about 40 cents per GB, it could cut into SanDisk’s margins. We currently forecast SanDisk’s margins to remain flat over current values. A conservative reduction in gross margins by 2-3 percentage points in both the flash cards and enterprise storage division from 2014 through 2016 could lead to a 3% downside to our $86 price estimate for SanDisk.

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  1. Toshiba, SanDisk Join 3-D Chip Race, Wall Street Journal, May 2014 [] []
  2. Toshiba, SanDisk Start Producing Smaller, Faster 15nm NAND Flash Memory, PC World, April 2014 []
  3. SanDisk And Toshiba Team Up To Create 3D SSDs, Computer World, May 2014 []
  4. Samsung Starts Mass Producing Industry’s First 32-Layer 3D V-NAND Flash Memory, The Korea Bizwire, May 2014 []
  5. Toshiba, SanDisk To Mass Produce High-Power ‘3D’ Memory, Economic Times, May 2014 []
  6. 3D NAND: To 10nm And Beyond, Semiconductor Manufacturing And Design, January 2014 []
  7. Samsung Produces First 3D NAND, Aims To Boost Densities, Extreme Tech, August 2013 []
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  • commented 7 years ago
  • Your description of 3D NAND (or V-NAND) is fundamentally flawed, and you're using terms like "card" and "chip" incorrectly. This may not matter for your purposes of investment advice, but it's still best not to propagate misinformation about how the technology works.

    You describe 3D NAND as "stacking the chips vertically", which implies multiple chips being stacked on top of each other. Chip-stacking (more accurately, "die-stacking", because the silicon dies are being stacked, then packaged into a chip or package) is and old and common technique used by all NAND manufacturers for many years. This is NOT 3D NAND. Virtually all NAND chips (i.e. the black plastic packages) sold in the past decade have multiple silicon die stacked on top of each other inside.

    3D NAND refers to stacking the actually memory cells within a single die, above the silicon surface. A normal planar (2D) NAND die has a grid of memory cells (not a "grid of chips") on the surface of the silicon. Each memory cell represents 1 bit of memory (technically one cell can represent multiple bits in MLC or TLC NAND, but the distinction is not important here) and has a single "floating gate" structure where the data is actually stored. Historically, all of gates are built, essentially, on the silicon surface. 3D NAND changes that by building floating gates on top of each other, vertically, above the silicon. This is the new, hard part, because it requires building many new layers above the silicon, and because it's harder to access and control (to read or write) the cells when they're stacked into a 3D grid.

    The stacks of memory cells can be 16, 32, or even 64 to 128 or higher (theoretically), whereas there was only 1 cell in (roughly) the same area on a planer die. Since the increase in bit-storage is so great, manufacturers can use older, larger, more mature processes, which I believe is what you're referring to as "do not require extremely precise lithography." In fact, 3D NAND does require extremely precise lithography. But, because of the huge increase in storage per unit-area, the lithography used (i.e. the process node, or technology node) can be much larger and the overall storage per die will still increase greatly. Older, more mature process nodes, like 40nm, are cheaper and the fabs have a lot of experience making them. But, the patterning of the lithography, i.e. the precision, must be very precise to make the 3D NAND work, and to generate good yields.

    After a die with 3D cells is built, then many of those die can again be stacked on top of each other and packaged into a single chip, as already happens with planer die. Eventually, stacking many TLC, 3D NAND die into a single chip will lead to staggering amounts of storage in a extremely small package.

    If you need technical reference, The Memory Guy (not me) has an excellent series on 3D NAND