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  • commented 4.0 months ago
  • tags: SSNLF STX WDC SNDK
  • Your description of 3D NAND (or V-NAND) is fundamentally flawed, and you're using terms like "card" and "chip" incorrectly. This may not matter for your purposes of investment advice, but it's still best not to propagate misinformation about how the technology works.

    You describe 3D NAND as "stacking the chips vertically", which implies multiple chips being stacked on top of each other. Chip-stacking (more accurately, "die-stacking", because the silicon dies are being stacked, then packaged into a chip or package) is and old and common technique used by all NAND manufacturers for many years. This is NOT 3D NAND. Virtually all NAND chips (i.e. the black plastic packages) sold in the past decade have multiple silicon die stacked on top of each other inside.

    3D NAND refers to stacking the actually memory cells within a single die, above the silicon surface. A normal planar (2D) NAND die has a grid of memory cells (not a "grid of chips") on the surface of the silicon. Each memory cell represents 1 bit of memory (technically one cell can represent multiple bits in MLC or TLC NAND, but the distinction is not important here) and has a single "floating gate" structure where the data is actually stored. Historically, all of gates are built, essentially, on the silicon surface. 3D NAND changes that by building floating gates on top of each other, vertically, above the silicon. This is the new, hard part, because it requires building many new layers above the silicon, and because it's harder to access and control (to read or write) the cells when they're stacked into a 3D grid.

    The stacks of memory cells can be 16, 32, or even 64 to 128 or higher (theoretically), whereas there was only 1 cell in (roughly) the same area on a planer die. Since the increase in bit-storage is so great, manufacturers can use older, larger, more mature processes, which I believe is what you're referring to as "do not require extremely precise lithography." In fact, 3D NAND does require extremely precise lithography. But, because of the huge increase in storage per unit-area, the lithography used (i.e. the process node, or technology node) can be much larger and the overall storage per die will still increase greatly. Older, more mature process nodes, like 40nm, are cheaper and the fabs have a lot of experience making them. But, the patterning of the lithography, i.e. the precision, must be very precise to make the 3D NAND work, and to generate good yields.

    After a die with 3D cells is built, then many of those die can again be stacked on top of each other and packaged into a single chip, as already happens with planer die. Eventually, stacking many TLC, 3D NAND die into a single chip will lead to staggering amounts of storage in a extremely small package.

    If you need technical reference, The Memory Guy (not me) has an excellent series on 3D NAND
    http://thememoryguy.com/what-is-3d-nand-why-do-we-need-it-how-do-they-make-it/ [ less... ]
    Your description of 3D NAND (or V-NAND) is fundamentally flawed, and you're using terms like "card" and "chip" incorrectly. This may not matter for your purposes of investment advice, but it's still best not to propagate misinformation about how the technology works. You describe 3D NAND as "stacking the chips vertically", which implies multiple chips being stacked on top of each other. Chip-stacking (more accurately, "die-stacking", because the silicon dies are being stacked, then packaged into a chip or package) is and old and common technique used by all NAND manufacturers for many years. This is NOT 3D NAND. Virtually all NAND chips (i.e. the black plastic packages) sold in the past decade have multiple silicon die stacked on top of each other inside. 3D NAND refers to stacking the actually memory cells within a single die, above the silicon surface. A normal planar (2D) NAND die has a grid of memory cells (not a "grid of chips") on the surface of the silicon. Each memory cell represents 1 bit of memory (technically one cell can represent multiple bits in MLC or TLC NAND, but the distinction is not important here) and has a single "floating gate" structure where the data is actually stored. Historically, all of gates are built, essentially, on the silicon surface. 3D NAND changes that by building floating gates on top of each other, vertically, above the silicon. This is the new, hard part, because it requires building many new layers above the silicon, and because it's harder to access and control (to read or write) the cells when they're stacked into a 3D grid. The stacks of memory cells can be 16, 32, or even 64 to 128 or higher (theoretically), whereas there was only 1 cell in (roughly) the same area on a planer die. Since the increase in bit-storage is so great, manufacturers can use older, larger, more mature processes, which I believe is what you're referring to as "do not require extremely precise lithography." In fact, 3D NAND does require extremely precise lithography. But, because of the huge increase in storage per unit-area, the lithography used (i.e. the process node, or technology node) can be much larger and the overall storage per die will still increase greatly. Older, more mature process nodes, like 40nm, are cheaper and the fabs have a lot of experience making them. But, the patterning of the lithography, i.e. the precision, must be very precise to make the 3D NAND work, and to generate good yields. After a die with 3D cells is built, then many of those die can again be stacked on top of each other and packaged into a single chip, as already happens with planer die. Eventually, stacking many TLC, 3D NAND die into a single chip will lead to staggering amounts of storage in a extremely small package. If you need technical reference, The Memory Guy (not me) has an excellent series on 3D NAND http://thememoryguy.com/what-is-3d-nand-why-do-we-need-it-how-do-they-make-it/
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